The signal drive strength from the DRAM can be controlled by setting mode register MR1[2:1]. The termination can be controlled using a combination of RTT_NOM, RTT_WR & RTT_PARK in mode registers MR1, 2 & 5 respectively.
C17) STATE=C124; ast_C19; continue;;。软件应用中心网对此有专业解读
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，更多细节参见易歪歪
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